projects / xen.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: bab5b8a) | patch
CPUIDLE: Handle C2 LAPIC timer & TSC stop
authorKeir Fraser <keir.fraser@citrix.com>
Mon, 22 Sep 2008 10:24:02 +0000 (11:24 +0100)
committerKeir Fraser <keir.fraser@citrix.com>
Mon, 22 Sep 2008 10:24:02 +0000 (11:24 +0100)
commit3724ccf9fa870fe57b543c353b0889bf3a9567a1
treec65841bae81284ee77bd5291bef53e5e30e5fc5etree | snapshot
parentbab5b8ad338015128fcfddd576f4614be1c45e76commit | diff
CPUIDLE: Handle C2 LAPIC timer & TSC stop

ACPI C2 is quite possible mapped to CPU C3 or deeper state, so
thinking from worst cases, enable C3 like entry/exit handling for C2
by default. Option 'lapic_timer_c2_ok' can be used to select simple C2
entry/exit only if the user make sure that LAPIC tmr & TSC will not be
stop during C2.

Signed-off-by: Wei Gang <gang.wei@intel.com>
xen/arch/x86/acpi/cpu_idle.c diff | blob | history
Unnamed repository; edit this file 'description' to name the repository.